‘Process and metrics before tools for better verification’
Chip-design teams are running into problems with verification because they are focused too much on tools and not enough on processes, Mentor Graphics chief scientist Harry Foster explained today at the...
View ArticleDVCon Europe focuses on systems design and verification
The program and registration details for a European version of DVCon, the verification conference, are now online. The Design and Verification Conference & Exhibition Europe (DVCon Europe) will...
View ArticleClik here to view.
Formal integration enhances bug-hunting for Cadence
Following the acquisition of Jasper Design Automation last year, Cadence Design Systems is widening the target base of applications for formal verification, covering tasks from bug hunting through...
View Article‘Process and metrics before tools for better verification’
Chip-design teams are running into problems with verification because they are focused too much on tools and not enough on processes, Mentor Graphics chief scientist Harry Foster explained today at the...
View ArticleDVCon Europe focuses on systems design and verification
The program and registration details for a European version of DVCon, the verification conference, are now online. The Design and Verification Conference & Exhibition Europe (DVCon Europe) will...
View ArticleClik here to view.
Formal integration enhances bug-hunting for Cadence
Following the acquisition of Jasper Design Automation last year, Cadence Design Systems is widening the target base of applications for formal verification, covering tasks from bug hunting through...
View Article
